System and method for product yield prediction

ABSTRACT

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

BACKGROUND OF THE INVENTION

[0001] The present invention pertains to fabrication of integratedcircuits and more particularly to systems and methods for improvingfabrication yields.

[0002] The fabrication of integrated circuits is an extremely complexprocess that may involve hundreds of individual operations. Basically,the process includes the diffusion of precisely predetermined amounts ofdopant material into precisely predetermined areas of a silicon wafer toproduce active devices such as transistors. This is typically done byforming a layer of silicon dioxide on the wafer, then utilizing aphotomask and photoresist to define a pattern of areas into whichdiffusion is to occur through a silicon dioxide mask. Openings are thenetched through the silicon dioxide layer to define the pattern ofprecisely sized and located openings through which diffusion will takeplace. After a predetermined number of such diffusion operations havebeen carried out to produce the desired number of transistors in thewafer, they are interconnected as required by interconnection lines.These interconnection lines, or interconnects as they are also known,are typically formed by deposition of an electrically conductivematerial which is defined into the desired interconnect pattern by aphotomask, photoresist and etching process. A typical completedintegrated circuit may have millions of transistors contained with a 0.1inch by 0.1 inch silicon chip and interconnects of submicron dimensions.

[0003] In view of the device and interconnect densities required inpresent day integrated circuits, it is imperative that the manufacturingprocesses be carried out with utmost precision and in a way thatminimizes defects. For reliable operation, the electricalcharacteristics of the circuits must be kept within carefully controlledlimits, which implies a high degree of control over the myriad ofoperations and fabrication processes. For example, in the photoresistand photomask operations, the presence of contaminants such as dust,minute scratches and other imperfections in the patterns on thephotomasks can produce defective patterns on the semiconductor wafers,resulting in defective integrated circuits. Further, defects can beintroduced in the circuits during the diffusion operations themselves.Defective circuits may be identified both by visual inspection underhigh magnification and by electrical tests. Once defective integratedcircuits have been identified, it is desired to take steps to decreasethe number of defective integrated circuits produced in themanufacturing process, thus increasing the yield of the integratedcircuits meeting specifications.

[0004] In the past, many of the defects which caused poor yield inintegrated circuits were caused by particulate contaminants or otherrandom sources. Increasingly, many of the defects seen in modernintegrated circuit processes are not sourced from particulates or randomcontaminants, especially in the earlier stages of process development oryield ramping, but rather stem from very systematic sources. Examples ofthese systematic defect sources include printability problems from usingaggressive lithography tools, poly stringers from poorly formedsilicides, gate length variation from density driven and opticalproximity effects.

[0005] In attempting to decrease the number of defective integratedcircuits produced in the manufacturing process, thus increasing theyield, one is faced with the fact that any one or more of possiblyseveral hundred processing steps may have caused a particular circuit tobe defective. With such a large number of variables to work with, it canbe extremely difficult to determine the exact cause or causes of thedefect or defects in a particular circuit thereby making itextraordinarily difficult to identify and correct the yield detractingprocess operations. Detailed inspection of the completed integratedcircuits may provide some indication of which process operation may havecaused the circuits to be defective. However, inspection equipment oftendoes not capture many of the systematic defect sources and/or the toolscan be difficult to tune, optimize, or use effectively and reliably.Furthermore, inspection equipment, especially in recent technologies isoften plagued with many false alarms or nuisance defects, as they areknown, which serve to frustrate any attempts to reliably observe truedefects or sources of defects.

[0006] It is typically discovered that, once a particular problem hasbeen identified at final test after completion of the fabrication cycle,it can be confirmed that a problem in a particular process operation didexist at the time that operation was carried out, which could have beenweeks or even months earlier. Thus the problem might be corrected shellafter the fact. At this time, different process operations may becausing problems. Thus, after the fact analysis of defective integratedcircuits and identification of process operations causing thesedefective products is severely limited as a means for improving theoverall yield of integrated circuits.

[0007] A number of attempts to predict yields instead of conductingunsatisfactory after the fact analysis have been made with varyingdegrees of success. Thus, there is a need for an improved system andmethod for integrated circuit product yield prediction.

SUMMARY OF THE INVENTION

[0008] A system and method for predicting yield of integrated circuitsincludes at least one type of characterization vehicle whichincorporates at least one feature which is representative of at leastone type of feature to be incorporated in the final integrated circuitproduct. The characterization vehicle is subjected to at least one ofthe process operations making up the fabrication cycle to be used infabricating the integrated circuit product in order to produce a yieldmodel. The yield model embodies a layout as defined by thecharacterization vehicle and preferably includes features whichfacilitate the gathering of electrical test data and testing ofprototype sections at operating speeds. An extraction engine extractspredetermined layout attributes from a proposed product layout.Operating on the yield model, the extraction engine produces yieldpredictions as a function of layout attributes and broken down by layersor steps in the fabrication process. These yield predictions are thenused to determine which areas in the fabrication process require themost improvement.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a block diagram depicting the steps performed by apreferred embodiment of the system of the present invention.

[0010]FIG. 2 is a block diagram depicting additional steps performed bythe system of the present invention to effect a feedback loop.

[0011]FIG. 3 is an image of an illustrative short flow mask comprising asingle lithographic layer.

[0012]FIG. 4 depicts pad frames on an exemplary metal short flow chip.

[0013]FIG. 5 depicts pads within each pad frame depicted in FIG. 4.

[0014]FIG. 6 depicts two types of pad frame structures which contain vander Pauw structures.

[0015]FIG. 7 depicts locations, on the exemplary chip, of the pad framescontaining the van der Pauw structures.

[0016]FIG. 8 depicts an exemplary van der Pauw structure.

[0017]FIG. 9 depicts exemplary locations of nest defect sizedistribution structures on an exemplary metal short flow chip.

[0018]FIG. 10 depicts an exemplary nest defect size distributionstructure.

[0019]FIG. 11 depicts an exemplary Kelvin critical dimension structure.

[0020]FIG. 12 depicts exemplary locations of Kelvin structures on anexemplary metal short flow chip.

[0021]FIG. 13 depicts exemplary locations of snakes and combs on anexemplary metal short flow chip.

[0022]FIG. 14 depicts exemplary snake and comb structures used in anexemplary metal short flow chip.

[0023]FIG. 15 depicts examples of variations of border structures usedin an exemplary metal short flow chip.

[0024]FIG. 16 depicts exemplary locations of border structures on anexemplary metal short flow chip.

[0025]FIG. 17 depicts exemplary locations of scanning electronmicroscope structures on an exemplary metal short flow chip.

[0026]FIG. 18 depicts an exemplary test structure illustrating ashortable area.

[0027]FIG. 19 depicts an exemplary test pattern for examining the yieldof T-shaped endings at the ends of lines.

[0028]FIG. 20 depicts an exemplary nest structure for extracting defectsize distributions.

[0029]FIG. 21 depicts a plot for determining the rate at which defectsdecay over size.

[0030]FIG. 22(a), 22(b) and 22(c) depict, respectively, linewidth,linespace and pattern density distributions for a metal-1 layer of asample product layout.

DETAILED DESCRIPTION

[0031] Referring now to FIG. 1, there is shown a block diagram depictingthe steps performed by a system, generally designated 10, for predictingintegrated circuit yields in accordance with the present invention. Thesystem 10 utilizes at least one type of characterization vehicle 12. Thecharacterization vehicle 12 preferably is in the form of softwarecontaining information required to build an integrated circuit structurewhich incorporates at least one specific feature representative of atleast one type of feature to be incorporated into the final product. Forexample, the characterization vehicle 12 might define a short flow testvehicle of a single lithographic layer for probing the health andmanufacturability of the metal interconnection module of the processflow under consideration. The structures need to be large enough andsimilar enough to the actual product or type of products running in thefabrication-process to enable a reliable capture or fingerprint of thevarious maladies that are likely to affect the product during themanufacturing. More specific examples and descriptions of short flowsand the structures embodied in them are described below.

[0032] Short flow is defined as encompassing only a specific subset ofthe total number of process steps in the integrated circuit fabricationcycle. For example, while the total fabrication cycle might contain upto 450 or more process steps, a characterization vehicle such as onedesigned to investigate manufacturability of a single interconnectionlayer would only need to include a small number, for example 10 to 25process steps, since active devices and multiple interconnection layersare not required to obtain a yield model or allow accurate diagnosis ofthe maladies afflicting these steps associated with a singleinterconnection layer in the process flows.

[0033] The characterization vehicle 12 defines features which match oneor more attributes of the proposed product layout. For example, thecharacterization vehicle 12 might define a short flow test vehiclehaving a partial layout which includes features which are representativeof the proposed product layout (e.g. examples of line size, spacing andperiodicity; line bends and runs; etc.) in order to determine themaladies likely afflicting those specific design types and causing yieldloss.

[0034] The characterization vehicle 12 might also define one or moreactive regions and neighboring features of the proposed design in orderto explore impact of layout neighborhood on device performance andprocess parameters; model device parameters as a function of layoutattributes; and determine which device correlate best with productperformance. Furthermore, by constructing and analyzing a sufficientnumber of short flow vehicles such that the range of all possible or amajor subset of all the modular components of the entire process isexercised, a full evaluation of many if not all of the yield problemswhich will afflict the specific product manufactured can be uncovered,modeled, and/or diagnosed.

[0035] In addition to providing information for assessing and diagnosingyield problems likely to be seen by the product(s) under manufacture,the characterization vehicle is designed to produce yield models 16which can be used for accurate yield prediction. These yield models 16can be used for purposes including, but not limited to, productplanning, prioritizing yield improvement activities across the entireprocess, and modifying the original design of the product itself to makeit more manufacturable.

[0036] The majority of the test structures in the characterizationvehicle 12 contemplated in the invention are designed for electricaltesting. To this end, the reliability of detecting faults and defects inthe modules evaluated by each characterization vehicle is very high.Inspection equipment cannot deliver or promise this high degree ofreliability. Furthermore, the speed and volume of data collection isvery fast and large respectively since electrical testing is fast andcheap. In this way, statistically valid diagnosis and/or yield modelscan be realized.

[0037] The characterization vehicle 12 is preferably in the form of aGDS 2 layout on a tape or disc which is then used to produce a reticleset. The reticle set is used during the selected portions of thefabrication cycle 14 to produce the yield model 16. Thus the yield model16 is preferably constructed from data measured from at least a portionof a wafer which has undergone the selected fabrication process stepsusing the reticle set defined by the characterization vehicle 12.

[0038] The yield model 16 not only embodies the layout as defined by thecharacterization vehicle, it also includes artifacts introduced by thefabrication process operations themselves. The yield model 16 may alsoinclude prototype architecture and layout patterns as well as featureswhich facilitate the gathering of electrical test data and testingprototype sections at operating speeds which enhances the accuracy andreliability of yield predictions.

[0039] An extraction engine 18 is a tool for extracting layoutattributes from a proposed product layout 20 and plugging thisinformation into the yield model 16 to obtain a product yield prediction22. Such layout attributes might include, for example, via redundancy,critical area, net length distribution, and line width/spacedistribution. Then, given layout attributes from the proposed productlayout 20 and data from yield models 16 which have been fabricated basedupon information from the characterization vehicles 12, product yield 22is predicted. Using the system and method of the present invention, thepredictable product yield obtainable can be that associated with eachdefined attribute, functional block, or layer, or the resultant yieldprediction for the entire product layout.

[0040] Referring now to FIG. 2, there is shown a block diagram of thesystem for predicting integrated circuit yields 10 in accordance withthe present invention additionally comprising a feedback loop, generallydesignated 24, for extracting design attributes 26 from product layout20 by means of extraction engine 28. In accordance with this feature ofthe present invention, the characterization vehicle 12 is developedusing attributes of the product layout 20. In this case, attributes ofthe product layout are extracted, making sure that the range ofattributes are spanned in the characterization vehicle 12. For example,the product layout is analyzed to determine line space distribution,width distribution, density distribution, the number of island patterns,in effect developing a subset of the entire set of design rules of thefabrication process, which subset is applicable to the particularproduct layout under consideration. With respect to patterns, theproduct layout analysis would determine the most common pattern, thesecond most common pattern, and so forth. These would be extracted bythe extraction engine 28 yielding design attributes 26 encompassing allof these patterns for inclusion into the characterization vehicle 12.With respect to densities, if the analysis of the product layout revealsthat the density of a first metal is from 10% to 50%, then thecharacterization vehicle would include the entire range of 10% to 50%for the first metal.

[0041] One type of characterization vehicle is a metal short flowcharacterization vehicle. The purpose of the metal short flowcharacterization vehicle is to quantify the printability andmanufacturability of a single interconnect layer. Usually a metal shortflow is run very early in the process since metal yield is crucial forhigh product yield, is often very difficult to obtain, and consists ofonly a few independent processing steps. Conducting short flowexperiments using a metal short flow mask, enables experiments andanalysis to be carried out in rapid succession to eliminate or minimizeany systematic yield or random defect yield issue that is detectedwithout having to wait for complete flow runs to finish.

[0042] Referring to FIG. 3, there is shown an image of a typical andillustrative metal short flow mask, generally designated 30, whichconsists of a single lithographic layer. The mask 30 is used to define asingle metal layer on a chip, and the exemplary chip 32 depicted in FIG.3 is as large as the stepper can accomodate which is, in this example,approximately 22 mm×22 mm in size. It is divided into four quadrants,42, 4, 46 and 48 as shown in FIG. 4, each containing one or more of sixbasic structures: (i) Kelvin metal critical dimension structures; (ii)snake and comb structures; (iii) nest defect size distributionstructures; (iv) van der Pauw structures; (v) OPC evaluation structures;and (vi) classical scanning electron microscopy (SEM) structures.

[0043] Approximately 50% of the chip area is devoted to nest structuresfor extraction of defect size distribution while 40% of the chip area isdevoted to detecting systematic yield loss mechanisms and measuringparametric variation. FIG. 3 also depicts the location of pad frames 34on the chip. In the embodiment described herein, there are 131 padframes on the chip, with each pad frame 34 comprising thirty-two pads asshown in FIG. 5. The pads within each pad frame 34 provide electricalconnection points which are contacted by external test equipment asrequired by a test program to be described later.

[0044] The van der Pauw test structures 82 used in this chip (see FIG.8) are four terminal square structures which take advantage of thesymmetry of the structure for direct determination of the sheetresistance. Accurate determination of sheet resistance is a requirementfor measurement of linewidth variation. The van der Pauw structures 82are arranged in two different frame types: mixed 62 (see FIG. 6A) andVDP 1 64 (see FIG. 6B). FIG. 7 depicts the location of the pad frames 72containing the van der Pauw structures in the exemplary metal short flowchip described herein. In this exemplary chip, the van der Pauwstructures occupy less than 1% of the chip area. In the van der Pausesstructures the line width (LW) and the LW tap (see FIG. 8) are theparameters that are varied. Table I shows the variations in the van derPauw structures in the exemplary metal short flow chip described herein.TABLE I LW (μm) LW tap (μm) 1 (DR) 1 (DR) 1.1 1.1 5 1 10 2 25 5 35 7 353.5 50 5

[0045] The nest defect size distribution structures are arrays of nestedcontinuous lines designed for opens and shorts detection and for theextraction of defect size distribution. Line width and space between theline are the parameters that are varied to facilitate the extraction ofdefect size distribution. In the embodiment described herein, thesestructures occupy 50% of the chip area at locations 92 and 94 shown inFIG. 9 and have fourteen variants in a total of ten cells 96. The amountof area these structures can occupy needs to be large enough toaccurately detect less than 0.25 defects/cm² for one wafer. The numberof variants typically include the design rule (DR), slightly below DR,slightly above DR and substantially above DR. Therefore, for example, ifDR is 1.0 μm for line spacing, the plots might be for 0.9, 1.1, 1.3 and2.5 as shown in Table II. TABLE II Line Width = Length Space (μm) (cm)0.9 39.6 1.0 (DR) 36 1.1 33 1.3 28.2 2.5 24.6

[0046] Each cell is split into six sub-cells to reduce the lineresistance to reasonable levels (less than 250 kΩ) and to minimize theincidence of multiple defects per cell. In this embodiment, there aresixteen snakes per cell. An exemplary nest defect size distributionstructure itself, generaly designated 1002, is depicted in FIG. 10. Thenest defect size distribution structures are designed such that the linewidth (LW) is equal to the spacing (S) between the lines to simplifysubsequent analysis of data.

[0047] The Kelvin metal critical dimension (CD) structures are made upof a continuous straight line with terminal connections at each end.These structures allow for precise line resistance measurements which,in conjunction with the sheet resistance determined from the van derPauw structures, allow for the determination of Kelvin line width. Thesestructures are designed primarily to determine the variation in theelectrical critical dimension. An exemplary Kelvin critical dimensionstructure, generally designated 110, is depicted in FIG. 11. To studythe impact of optical proximity effect on the variability in theelectrical critical dimension, local neighborhood structures are varied.The parameters varied for the local neighborhood are the number 112,line width 114 and space 116 of the lines. The global environment 118around the Kelvin structures is also varied, primarily to study etchrelated effects on the electrical critical dimension (see FIG. 11).Parameters varied for global neighborhood are the density and area. Theglobal neighborhood structures can also serve other electricalmeasurement needs. For example, the yield of these structures can bemeasured so that not only metal critical dimension as a function ofenvironment is obtained, but also yield as a function of environment.FIG. 12 depicts the location of Kelvin structures 122 in the metal shortflow chip described herein. These locations are chosen to coveravailable area. Tables III through IX describe the variations in theKelvin structures used in the metal short flow chip described herein.These values were chosen as to cover the space identified in FIG. 22(a)through 22(b). For example, the pattern density is centered around 45%and the line width and spaces are in the range of 1.0 to 3.3 μm sincethis is where most of an exemplary product layout is centered. TABLE IIILine Spacing Number of Width (μm) (μm) Local Lines Fixed Parameters 0.750.75 6 Local line width = 1 μm 0.9 0.9 Density = 45% 1 μm (DR) 1.0 (DR)Line width of comb = 1.3 μm 1.1 1.1 Dx max = 400 (μm) 1.3 1.3 Dy max =400 (μm) 2.5 2.5 3.3 3.0 10 3.3 10 50

[0048] TABLE IV Line Space Number of Width (μm) ratio Local Lines FixedParameters 0.75 2 to 1 6 Local line width = 1 μm 0.9 3 to 1 2 Density =45% 1 (DR) Line width of comb = 1.3 μm 1.1 Dx max = 400 (μm) 1.3 Dy max= 400 (μm) 2.5 3.3 10

[0049] TABLE V Line Number of Local Line Spacing Width (μm) Local linesWidth (μm) (μm) Fixed Parameters 0.75 1 1 (DR) 1 (DR) Density = 0.450.9  2 1.3 1.3 Line width of comb = 1.3 μm 1 (DR) 4 Dx max = 400 (μm)1.1  Dy max = 400 (μm) 1.3  2.5  3.3  10  

[0050] TABLE IV Line Number LW Width Spacing of local comb (μm) (μm)lines Density (μm) Fixed Parameters 1.0 1.0 6 0 1.3 Dx max = 400 (μm)(DR) (DR) 2 0.2 10 Dy max = 400 (μm) 1.3 1.3 0.40 0.45 0.50

[0051] TABLE VII Line Spacing Line width Width (μm) (μm) local (μm)Fixed Parameters 0.9 1.0 (DR) 10 Number of local lines 2 1.0 (DR) 1.1 30Density 0.45 1.1 1.3 100 Line width comb 1.3 1.3 2.5 Dx max = 400 (μm)2.5 3.3 Dy max = 400 (μm) 3.3 10 10

[0052] TABLE VIII Line Spacing Width (μm) (μm) Fixed Parameters 1.0 (DR)1.0 (DR) Number of local lines 6 1.1 1.1 Density-0.45 1.3 1.3 Line widthcomb 1.3 2.5 2.5 Dx_max = 400 (μm) 10 3.0 Dy_max = 400 (μm) 5.3 Linewidth local 1.3

[0053] TABLE IX Line Width Spacing Local (μm) (μm) density Dx_max FixedParameters Comments 0.75 Number of local lines 0 Isolated Kelvins 0.9Density 0 1.0 (DR) Line width comb 0 1.1 Line width local 0 1.3 Dx_max =400 (μm) 2.5 Dy_max = 400 (μm) 3.3 10 10 2.5 Line width = 1.0 (μm) Local20 3.5 Local line width = 1.0 neighborhood (μm) 30 4.5 Number of locallines 2 size 40 5.5 Density 0.45 50 6.5 Comb line width 1.3 60 7.5Dx_max = 400 (μm) 70 8.5 Dy_max = 400 (μm) 80 9.5 25 Line width 1.0Global 50 Line width local 1.0 neighborhood 100 Space 1.0 size 150Number of local lines 6 200 Density 0.45 250 Line width comb 1.3 300Dy_max 400 (μm) Line Width Spacing N_local Dx_max Fixed ParametersComments 1.0 (DR) 1.0 (DR) 6 D_local 5 Standards 1.3 1.3 6 Line widthcomb 1.3 1.0 40 2 0.45 1.3 40 2

[0054] The snake, comb and snake & comb structures are designedprimarily for the detection of shorts and opens across a wide variety ofpatterns. Snakes are used primarily for the detection of opens and canalso be used for monitoring resistance variation. Combs are used formonitoring shorts. Shorts and opens are fundamental yield lossmechanisms and both need to be minimized to obtain high product yield.FIG. 13 shows the location of snakes and combs 1302 in the metal shortflow chip described herein. Quadrant one 1304 also contains snakes 1402and combs 1404 nested within the Kelvin structures as shown, for examplein FIG. 14. Line width (LW) and space (S), see FIG. 14, are theparameters varied on these structures to study their impact on shortsand opens. Tables X through XIII describe the variations of snake andcomb structures used in the metal short flow chip described herein.Again, the parameters were chosen such that the space covered in linewidth, line space, and density is similar to that seen in the exampleproduct layout, as shown in FIG. 22(a) through 22(c). TABLE X LW_combSpace LW_snake (μm) (μm) (μm) Fixed Parameters 20 0.9 1.0 Dx_max = 200(μm) 50 1.0 (DR) (DR) Dy_max = 400 (μm) 100 1.1 200 1.3 300 2.5 3.0 3.310 20 1.3 1.3 50 3.1 100 3.3 200 3.5 300 10

[0055] TABLE XI LW_comb Space (μm) (μm) Fixed Parameters 0.75 0.75Dx_max = 200 (μm) 0.9 0.9 Dy_max = 400 (μm) 1.0 (DR) 1.0 (DR) 1.1 1.11.3 1.2 2.0 1.3 3.3 2.5 10 3.0 3.3 10

[0056] TABLE XII Line Width (μm) Fixed Parameters 0.75 Dx_max = 200 (μm)0.9 Dy_max = 400 (μm) 1.0 (DR) 10 (μm) 1.1 1.3 2.5 3.3 1.0

[0057] TABLE XIII LW (μm) Space (μm) Fixed Parameters 20 0.7 Dx_max =400 μm 50 1.0 (DR) Dy_max = 200 μm 100 1.1 200 1.3 500 2.5 2.7 3.0 3.3 510

[0058] Border and fringe structures are designed to study the impact ofoptical proximity correction (OPC) structures on shorts. These opticalproximity corrections are usually added to improve via yields. However,it is necessary to check metal short yield with and without theseborders to ensure that there is no detrimental impact to short yield.Borders 1502 are placed both at the end of the comb lines and in theinterior of comb structures, generally designated 1504, as shown in FIG.15. FIG. 16 shows the location of border structures, generallydesignated 1602, in the metal short flow chip described herein.

[0059] Scanning electron microscopy (SEM) structures are used fornon-electrical measurements of line width top down or cross sectionalSEM. For the SEM bars in the metal short flow chip described herein theline width is the same as the spacing between the lines in accordancewith traditional SEM techniques. FIG. 17 depicts the location of the SEMstructures 1702 in the metal short flow chip described herein. Thestructures are placed at the bottom of each quadrant 1704, 1706, 1708and 1710 of the embodiment depicted since this is where space wasavailable.

[0060] In FIGS. 3 through 17, and accompanying text, an examplecharacterization vehicle for metal yield improvement has been described.Other characterization vehicles for via, device, suicides, poly, el al,are often designed and utilized. However, the procedure and techniquesfor designing them are the same. For purposes of illustration, theexample metal characterization vehicle will be carried through onextraction engines and yield models.

[0061] The extraction engine 18 has two main purposes: (1) it is used indetermining the range of levels (e.g. linewidth, linespace, density) touse when designing a characterization vehicle. (2) It is used to extractthe attributes of a product layout which are then subsequently used inthe yield models to predict yield. (1) has already been described abovewith reference to how the line width, space and density of the snake,comb and Kelvin structures were chosen in the example characterizationvehicle. Thus, most of the following discussion focuses on (2).

[0062] Since there are nearly infinite numbers of attributes that can beextracted from the product layout, it is impossible to list or extractall of them for each product. Thus, a procedure is required to guidewhich attributes should be extracted. Usually, the characterizationvehicle drives which attributes to extract. The process consists of:

[0063] 1. List all structures in the characterization vehicle

[0064] 2. Classify each structure into groups or families such that allstructures in the family form an experiment over a particular attribute.For example, in the metal characterization vehicle discussed above, atable of family classifications might be: Family Attributes ExploredNest structures Basic defectivity over a few linewidths and spacesSnakes and Combs Yield over wide range of linewidths and spacesincluding very large widths next to small spaces and very large spacesnext to small widths. Kelvin-CD + CD variation across density,linewidth, and van der Pauws linespace. Border structures Effect ofdifferent OPC schemes on yield.

[0065] 3. For each family, determine which attributes must be extractedfrom the product layout. The exact attributes to choose are driven fromwhich attributes are explored. For example, if a particular familyexplores yield over different ranges of space, then either a histogramof spaces or the shortable area for each space must be extracted. Forthe above example, the required list of attributes might be: FamilyAttributes Explored Attributes to Extract from Product Layout (A) Neststructures Basic defectivity over a few Critical area curves. linewidthsand spaces. (B) Snakes and combs Yield over wide range of Shortable areaand/or instance linewidths and spaces counts for each line width andincluding . . . space explored in the characterization vehicle. (C)Kelvin-CD and CD variation across density, Histograms of patterndensity, van der Pauws linewidth, and space linewidth, and linespace(similar to example shown in FIG. 22) (D) Border structures Effect ofdifferent OPC For each OPC scheme selected schemes on yield to use onproduct layout, the shortable area or instance count.

[0066] 4. Use the attributes extracted in the appropriate yield modelsas previously described.

[0067] For other characterization vehicles, the families and requiredattributes will obviously be different. However, the procedure andimplementation is similar to the example described above.

[0068] As previously stated, the yield model 16 is preferablyconstructed from data measured from at least a portion of a wafer whichhas undergone the selected fabrication process steps using the reticleset defined by the characterization vehicle 12. In the preferredembodiment, the yield is modeled as a product of random and systematiccomponents:$Y = {( {\prod\limits_{i = 1}^{n}{Ys}_{i}} )( {\prod\limits_{j = 1}^{m}{Yr}_{j}} )}$

[0069] The methods and techniques for determining Ys_(i) and Yr_(j) areas follows.

[0070] Systematic Yield Modeling

[0071] Since there are so many types of systematic yield loss mechanismsand they vary from fab to fab, it is not practicable to list everypossible systematic yield model. However, the following describes twovery general techniques and gives an example of their use especiallywithin the context of characterization vehicles and the methodologydescribed herein.

[0072] Area Based Models

[0073] The area based model can be written as:${Ys}_{i} = \lbrack \frac{Y_{o}(q)}{Y_{r}(q)} \rbrack^{{A{(q)}}/{A_{0}{(q)}}}$

[0074] Where q is a design factor explored in the characterizationvehicle such as line width, line space, length, ratio of width/space,density, etc. Y_(o)(q) is the yield of a structure with design factor qfrom the characterization vehicle. A_(o)(q) is the shortable area ofthis structure and A(q) is the shortable area of all instances of type qon the product layout. Y_(r)(q) is the predicted yield of this structureassuming random defects were the only yield loss mechanism. Theprocedure for calculating this quantity is described below in connectionwith random yield modeling.

[0075] The definition of shortable area is best illustrated with theexample shown in FIG. 18. This type of test structure can be used todetermine if the fab is capable of yielding wide lines that have a bendwith a spacing of s. In this sample test structure, a short is measuredby applying a voltage between terminal (1) and (2) and measuring thecurrent flowing from terminal (1) to (2). If this current is larger thana specified threshold (usually 1-100 nA), a short is detected. Theshortable area is defined to be the area where if a bridging occurs, ashort will be measured. In the example of FIG. 18, the shortable area isapproximately x*s). The A(q) term is the shortable area of alloccurrences of the exact or nearly exact patten (i.e. a large line witha spacing of s and a bend of 45 degrees) shown in FIG. 18 in a productlayout. The Yr(q) term is extracted by predicting the random yield limitof this particular structure using the critical area method describedbelow.

[0076] It is important to realize that the effectiveness of this modelis only as good as the number of structures and size of structuresplaced on the characterization vehicle. For example, if the angled bendtest structure shown in FIG. 18 were never put on the characterizationvehicle or was not placed frequently enough to get a meaningful yieldnumber, then there would be no hope of modeling the yield loss of wideline bends on the product layout. While it is difficult to defineexactly how many of how big the test structure should be on thecharacterization vehicle, practical experience has shown that the totalshortable area of each test structure on the characterization vehicleshould ideally be such that A(q)/Ao(q)<10.

[0077] The above discussion has concentrated on shorts since theygenerally tend to dominate over open yield loss mechanisms. However,open yield loss mechanisms can be modeled equally well with this yieldmodel so long as shortable area is replaced by open causing area.

[0078] Instance Based Yield Model

[0079] The general form of the instance based yield model is:${Ys}_{i} = \lbrack \frac{Y_{o}(q)}{Y_{r}(q)} \rbrack^{{N_{i}{(q)}}/{N_{0}{(q)}}}$

[0080] Where Yo(q) and Yr(q) are exactly the same as in the area basedyield model. Ni(q) is the number of times the unit cell pattern or verysimilar unit cell pattern to the test pattern on the characterizationvehicle appears on the product layout. No(q) is the number of times theunit cell pattern appears on the characterization vehicle.

[0081] For example, FIG. 19 shows a simple test pattern for examiningthe yield of T-shaped endings at the ends of lines near a space of s.This test pattern is measured by applying a voltage across terminals (1)and (2) and measuring the shorting current. If this pattern was repeated25 times somewhere on the characterization vehicle, then No(q) would be25×5=125 since there are five unit cells per each test structure.

[0082] If the number of times this unit cell occurs with a spacing of snear it is extracted from the product layout, the systematic yield ofthis type of structure can be predicted. For example, if there are fivestructures with 500 unit cells in each structure then No(q)=2500. IfNi(q) from some product was 10,000 and a yield of the test structures onthe characterization vehicle of 98.20% was measured. Using thetechniques described below, Yr(q) can be estimated as 99.67%. Usingthese numbers in the equation:${Ys}_{i} = {\lbrack \frac{0.9820}{0.9967} \rbrack^{10000/2500} = {92.84\%}}$

[0083] Random Yield Modeling

[0084] The random component can be written as:Y_(r) = ^(−∫_(x₀)^(∞)CA(x) × DSD(x)x)

[0085] Where CA(x) is the critical area of defect size x and DSD(x) isthe defective size distribution, as also described in “Modeling ofLithography Related Yield Losses for CAD of VSLI Circuits”, W. Maly,IEEE Trans. on CAD, July 1985, pp161-177, which is incorporated byreference as if fully set forth herein. Xo is the smallest defect sizewhich can be confidently observed or measured. This is usually set atthe minimum line space design rule. The critical area is the area whereif a defect of size x landed, a short would occur. For very small x, thecritical area is near 0 while very large defect sizes have a criticalarea approaching the entire area of the chip. Additional description ofcritical area and extraction techniques can be found in P. K. Nag and W.Maly, “Yield Estimation of VLSI Circuits,” Techcon90, Oct. 16-18, 1990.San Jose; P. K. Nag and W. Maly, “Hierarchical Extraction of CriticalArea for Shorts in Very Large ICs,” in Proceedings of The IEEEInternational Workshop on Detect and Fault Tolerance in VLSI Systems,IEEE Computer Society Press 1995, pp. 10-18; I. Bubel, W. Maly, T. Waas,P. K. Nag, H. Hartmann, D. Schmitt-Landsiedel and S. Griep, “AFFCCA: ATool for Critical Area Analysis with Circular Defects and LithographyDeformed Layout,” in Proceedings of The IEEE International Workshop onDetect and Fault Tolerance in VLSI Systems, IEEE Computer Society Press1995, pp. 19-27; C. Ouyang and W. Maly, “Efficient Extraction ofCritical Area in Large VISI ICs,” Proc. IEEE International Symposium onSemiconductor Manufacturing, 1996, pp. 301-304; C. Ouyang, W. Pleskacz,and W. Maly, “Extraction of Critical Area for Opens in Large VLSICircuits,” Proc. IEEE International Workshop on Defect and FaultTolerance of VLSI Systems, 1996, pp. 21-29, all of which references areincorporated in this detailed description as if fully set forth herein.

[0086] The defect size distribution represents the defect density ofdefects of size x. There are many proposed models for defect sizedistributions (see, for example, “Yield Models—Comparative Study”, W.Maly, Defect and Fault Tolerance in VLSI Systems, Ed. by C. Stapper, etal, Plenum Press, New York, 1990; and “Modeling of Integrated CircuitDefect Sensitivities”, C. H. Stapper, IBM J. Res. Develop., Vol. 27, No.6, November, 1983, both of which are incorporated by reference as iffully set forth herein), but for purposes of illustrations, the mostcommon distribution: ${{DSD}(x)} = \frac{D_{o} \times k}{x^{p}}$

[0087] will be used where Do represents the total number of defects/cm²greater than x_(o) observed. P is a unitless value which represents therate at which defects decay over size. Typically, p is between 2 and 4.K is a normalization factor such that${\int_{x_{o}}^{\infty}{\frac{k}{x^{p}}{x}}} = 1$

[0088] The following two sections describe techniques for extractingdefect size distributions from characterization vehicles.

[0089] The Nest Structure Technique

[0090] The nest structure is designed for extracting defect sizedistributions. It is composed of N lines of width w and space s as shownin FIG. 20. This structure is tested by measuring the shorting currentbetween lines 1 and 2, 2 and 3, 3 and 4, . . . , and N−1 and N. Anycurrent above a given spec limit is deemed a short. In addition, openscan be testing by measuring the resistance of lines 1, 2, 3, . . . ,N−1, and N. Any resistance above a certain spec limit is deemed to be anopen line. By examining how many lines are shorted together the defectsize distribution can be determined.

[0091] If only two lines are shorted then the defect size must begreater than s and no larger than 3w+2s. Any defects smaller than s willnot cause a short at all while defects larger than 3w+2s are guaranteedto cause a short of at least 3 lines. For each number of lines shorted,an interval of sizes can be created. Number Lines Shorted Size Interval2 s to 3w + 2s 3 2s + w to 3s + 4w 4 3s + 2w to 4s + 5w . . . . . . N (N− 1)s + (N − 2)w to (N)s + (N + 1)w

[0092] It should be noted that the intervals overlap; thus, a defectsize distribution cannot be directly computed. This restriction onlyplaces a limit on p extraction. Thus, in order to estimate p, a pestimate is computed from the distribution from all the even numberlines and then from all the odd number lines. Finally, the two valuesare averaged together to estimate p. To extract p, the ln (number offaults for x lines shorted) vs log ([x−1]s+[x−2]w) is plotted. It can beshown that the slope of this line is −p. The Do term is extracted bycounting the number of failures at each grouping of lines and dividingby the area of the structure. However, for very large Do, this estimatewill be too optimistic. Additional information on extracing defect sizedistribution from structures similar to the test structures can befound, for example, in “Extraction of Defect Size Distribution in an ICLayer Using Test Structure Data”, J. Khare, W. Maly and M. E. Thomas,IEEE Transactions on Semiconductor Manufacturing, pp. 354-368, Vol. 7,No. 3, August, 1994, which is incorporated by reference as if fully setforth herein.

[0093] As an example, consider the following data taken from 1 wafer of100 dies: Number Lines Shorted Number of Failures 2 98 3 11 4 4 5 2 6 17 0 8 0

[0094] If the structure size is 1cm² then the Do would be98+11+4+2+1=133/(100*1)=1.33 defects/cm². Also, the plot of log (numberof failures) vs log ([x−1]s+[x−2]w) (see FIG. 21) shows that p=2.05.

[0095] The Comb Structure Technique

[0096] Assuming a comb of width=space=s, it can be shown that the yieldof this structure can be written as:ln [ln (Y)] = ln [−∫_(x_(o))^(∞)DSD(x) × CA(x)x] ∝ (1 − p) × ln (s)

[0097] Thus, from the slope of the plot of In[|ln(Y)|] vs. ln(s), p canbe estimated. The Do extraction technique is the same technique asmentioned above.

[0098] Yield Impact and Assessment

[0099] Once a sufficient number of characterization vehicles has beenrun and yield estimates are made for each characterization vehicle, theresults are placed in a spread sheet to enable prioritization of yieldactivities. Tables XIV through XVI are examples of information containedin such a spread sheet. It has been divided into sections of metalyield, poly and active area (AA) yield (Table XIV), contact and viayield (Table XV), and device yield (Table XVI). The columns on the leftindicate systematic yield loss mechanisms while the columns on the rightindicate random yield loss mechanisms. Although the exact type ofsystematic failure mechanisms vary from product to product, andtechnology by technology, examples are shown in Tables XIV through XVI.

[0100] Usually, targets are ascribed to each module listed in the spreadsheet. The further a module yield is away from a target, the moreemphasis and resources are devoted to fixing the problem. For example,if the target was set artificially at 95 percent for each module in theexample shown in Tables XIV through XVI, then clearly (M

2

M₃) vias (75.12%) followed by similar vias (M

1

M₂) (81.92%), M₁ shorts (82.25%), and contacts to poly (87.22%) arebelow target and, with vias (M

2

M₃) needing the most amount of work and contacts to poly needing theleast amount of work.

[0101] Within each module, it is also possible to tell where thegreatest yield loss is situated. That is, is it one particularsystematic mechanism being the yield down or is it merely a randomdefectivity problem, or is it some combination of the two? For example,as shown in Table XV, via (M

2

M₃) yield loss is clearly dominated by a systematic problem affectingvias connected to long metal runners on the M₃ level (77.40%). Vias from(M

1

M₂) are affected by the same problems (91.52%) in addition to a randomdefectivity problem (92.49%). Solving vias (M

1

M₂) yield problems would require fixing both of these problems.

[0102] As shown in Table XIV, M₁ yield loss is also dominated by arandom defectivity issue (85.23%) in addition to a systematic problemaffecting wide lines near small spaces (96.66%). Fixing both of theseproblems would be required for improving Metal 1. Similar conclusionscan be made for other modules in the spread sheet.

[0103] For the worst yielding modules, frequent running of furthercharacterization vehicles for this module would be required. Usually,splits will be done on these characterization vehicles to try andimprove and validate those improvements in module yield. For the moduleswhich are within target, routine monitoring of short flowcharacterization vehicles would still be required to validate that therehas been no down turn or other movement in module yield. However, thesecharacterization vehicles can be run less frequently than for thosemodules with known problems. TABLE XIV Opens and Shorts (Metal Layers)Systematic Yield Loss Mechanisms Shortable Random Yield Loss MechanismArea Instant Estimated Estimated (cm{circumflex over ( )}2) Count YieldDo P Yield Metal-1 Random Yield 0.7 defects/cm{circumflex over ( )}2 2.385.23% Wide lines near small space 0.034  96.66% Wide space near smalllines 0.00014  99.99% Yield for OPC structures 72,341  99.86% Bent lines492 100.00% Total for M1 82.25% Metal-2 Random Yield 0.35defects/cm{circumflex over ( )}: 1.92 97.45% Wide lines near small space0.00079  99.92% Wide space near small lines 0.000042 100.00% Yield forOPC structures 1040372  97.94% Bent lines 103 100.00% Total for M295.36% Metal-3 Random Yield 0.25 defects/cm{circumflex over ( )}: 2.0296.92% Wide lines near small space 0.0000034 100.00% Wide space nearsmall lines 0 100.00% Yield for OPC structures 352 100.00% Bent lines7942  99.92% Total for M3 96.84% Open and Shorts (Poly and AA Layer)Poly Random Yield (without silicide) 0.17 defects/cm{circumflex over( )}: 2.03 99.81% 89 71% Random Yield (with silicide) 4.34defects/cm{circumflex over ( )}: 4.56 89.54% from silicide Wide linesnear small space 0 100.00% Wide space near small lines 0.01203  98.80%Yield for OPC structures 0 100 00% Bent lines 786541  92.44% Over wideAA 0.034  96.66% Over narrow AA 0.101  99.00% Total for Poly 87.22% AARandom Yield (without silicide) 1.3 3.45 99.12% 99.60% Random Yield(with silicide) 1.7 3.02 98.72% from silicide Wide lines near smallspace 10952  99 96% Wide space near small lines 0 100.00% Total for AA98.70

[0104] TABLE XV Contacts and Vias Systematic Yield Loss MechanismsShortable Random Yield Loss Mechanism Area Instant Estimated FaultEstimated (cm{circumflex over ( )}2) Count Yield Rate Number YieldContact to Poly Random Yield (without silicide) 2.20E−09 3270432 99.28%99.71% Random Yield (with suicide) 3.10E−09 3270432 98.99% Yield forLong Runners (on M1) 11,921 100.00% Yield for Long Runners (on Poly) 0100.00% Yield for Redundant Vias 39421 100.00% Yield for very isolatedcontacts 7200 96.46% Total for Contact to Poly 94.80% Contact to n + AARandom Yield (without silicide) 2.20E−09 5270432 98.85% 99.53% RandomYield (with silicide) 3.10E−09 5270532 98.38% Yield for Long Runners (onM1) 75,324 99.99% Yield for Long Runners (on n + AA) 0 100.00% Yield forRedundant Vias 4032007 99.60% Yield for very isolated contacts 720099.93% Total for Contact to AA (n+) 96.78% Contact to p + AA RandomYield (without silicide) 2.20E−09 6093450 98.67% Random Yield (withsilicide) 3.10E−09 6093450 98.13% Yield for Long Runners (on M1) 96,73299.99% Yield for Long Runners (on p + AA) 0 100.00% Yield for RedundantVias 39421 100.00% Yield for very isolated contacts 7200 99.93% Totalfor Contact to AA (p+) 96.74% Vias M1 -> M2 Random Yield (single vias)1.10E−08 7093210 92.49% Yield for Long Runners (M2) 88640 91.52% Yieldfor Long Runners (M1) 97645 99.03% Yield for Redundant Vias 1100345696.91% Yield for Isolated Vias 119582 96.81% Total for Via M1-M2 81.92%Vias M2 -> M3 Random Yield (single vias) 3.10E−09 4002063 98.77% Yieldfor Long Runners (M3) 256128 77.40% Yield for Long Runners (M2) 10343296.97% Yield for Redundant Vias 7096230 99.29% Yield for Isolated Vias1024 99.99% Total for Via M2-M3 75.12%

[0105] TABLE XVI Devices Systematic Yield Loss Mechanisms ShortableRandom Yield Loss Mechanism Area Instant Estimated Fault Estimated(cm{circumflex over ( )}2) Count Yield Rate Number Yield NMOS RandomYield (Logic Xtor) 2.90E−09 1395228 99.60% Random Yield (SRAM Xtor)2.80E−09 2226720 99.38% S/D Shorts 1.00E−09 3621948 99.64% BentTransistors 1113360 99.89% Near Large AA 754000 99.92% Near Small AA1023452 99.90% Total for NMOS Transistors 98.33% PMOS Random Yield(Logic Xtor) 1.80E−09 1491003 99.73% Random Yield (SRAM Xtor) 3.10E−091113360 99.66% S/D Shorts 9.00E.10 2604363 99.77% Bent Transistors556680 99.94% Near Large AA 789092 99.92% Near Small AA 1309970 99.87%Total for PMOS Transistors 98.89%

I claim:
 1. A system for predicting yield of integrated circuitscomprising: a) at least one type of characterization vehicle includingat least one feature which is representative of at least one type offeature to be incorporated into a final integrated circuit product; b) ayield model which embodies a layout as defined by the characterizationvehicle, said yield model having been subjected to at least one of theprocess operations making up the fabrication cycle to be used infabricating the integrated circuit product; c) a product layout; and d)an extraction engine for extracting predetermined layout characteristicsfrom the product layout, which characteristics are used in connectionwith the yield model to produce a yield prediction.
 2. A system inaccordance with claim 1 wherein the characterization vehicle layoutcontains the same range of variation of each feature as appears on theproduct layout.
 3. A system in accordance with claim 2 wherein thecharacterization vehicle comprises a short flow test vehicle.
 4. Asystem in accordance with claim 3 wherein the characterization vehiclecomprises a short flow test vehicle having a partial layout includingfeatures which are representative of a proposed product layout.
 5. Asystem in accordance with claim 4 wherein the characterization-vehicledefines at least one active region and at lease one preselectedneighboring feature representative of a proposed product layout.
 6. Asystem in accordance with claim 3 wherein the characterization vehiclecomprises a metal short flow test vehicle.
 7. A system in accordancewith claim 6 wherein the metal short flow test vehicle includes at leastone basic structure.
 8. A system in accordance with claim 7 wherein saidat least one basic structure is selected from the group consisting of:a) Kelvin metal critical dimension structure; b) snake structure; c)comb structure; d) snake and comb structures; e) nest defect sizedistribution structure; f) van der Pauw structure; g) optical proximitycorrection structure; and h) scanning electron microscopy structure. 9.A system in accordance with claim 8 wherein the metal short flow testvehicle includes at least one basic structure in a single metal layer.10. A system in accordance with claim 8 wherein the metal short flowtest vehicle includes at least one basic structure in multiple metallayers.
 11. A system in accordance with claim 4 wherein the featureswhich are representative of a proposed product layout include at leastone via or contact.
 12. A system in accordance with claim 4 wherein thefeatures which are representative of a proposed product layout includeat least one active device.
 13. A system in accordance with claim 4wherein the features which are representative of a proposed productlayout includes at least one silicide region.
 14. A system in accordancewith claim 4 wherein the features which are representative of a proposedproduct layout includes at least one polysilicide or polysilicon region.15. A system in accordance with claim 1 wherein the extraction engine isalso used to determine a range of layout feature levels for use whendesigning a characterization vehicle.
 16. A system in accordance withclaim 15 wherein the layout feature range of levels includes line width,line space and line density.
 17. A method for predicting a yield for anintegrated circuits comprising: a) providing information for fabricatingat least one type of characterization vehicle having at least onefeature which is representative of at least one type of feature to beincorporated into a final integrated circuit product; b) fabricating acharacterization vehicle which embodies a yield model and layoutfeatures representative of the product employing at least one of theprocess operations making up the fabrication cycle to be used infabricating the integrated circuit product; c) providing a productlayout; d) extracting predetermined layout characteristics from theproduct layout; and e) using the extracted layout characteristics inconnection with the yield model to produce a yield prediction.
 18. Amethod in accordance with claim 17 wherein the characterization vehiclelayout contains the same range of variation of each feature as appearson the product layout.
 19. A method in accordance with claim 18 whereinthe characterization vehicle comprises a short flow test vehicle.
 20. Amethod in accordance with claim 19 wherein the characterization vehiclecomprises a short flow test vehicle having a partial layout includingfeatures which are representative of a proposed product layout.
 21. Amethod in accordance with claim 20 wherein the characterization vehicledefines at least one active region and at lease one preselectedneighboring feature representative of a proposed product layout.
 22. Amethod in accordance with claim 19 wherein the characterization vehiclecomprises a metal short flow test vehicle.
 23. A method in accordancewith claim 22 wherein the metal short flow test vehicle includes atleast one basic structure.
 24. A method in accordance with claim 23wherein said at least one basic structure is selected from the groupconsisting of: a) Kelvin metal critical dimension structure; b) snakestructure; c) comb structure; d) snake and comb structures; e) nestdefect size distribution structure; f) van der Pauw structure; g)optical proximity correction structure; and h) scanning electronmicroscopy structure.
 25. A method in accordance with claim 24 whereinthe metal short flow test vehicle includes at least one basic structurein a single metal layer.
 26. A method in accordance with claim 24wherein the metal short flow test vehicle includes at least one basicstructure in multiple metal layers.
 27. A method in accordance withclaim 20 wherein the features which are representative of a proposedproduct layout include at least one via or contact.
 28. A method inaccordance with claim 20 wherein the features which are representativeof a proposed product layout include at least one active device.
 29. Amethod in accordance with claim 20 wherein the features which arerepresentative of a proposed product layout includes at least onesilicide region.
 30. A method in accordance with claim 20 wherein thefeatures which are representative of a proposed product layout includesat least one polysilicide or polysilicon region.
 31. A method inaccordance with claim 17 wherein the extraction engine is also used todetermine a range of levels for use when designing a characterizationvehicle.
 32. A method in accordance with claim 31 wherein the range oflevels includes line width, line space and line density.
 33. A method inaccordance with claim 17 wherein the predetermined layoutcharacteristics are extracted from the product layout using a processwhich includes the steps of: a) listing all structures in thecharacterization vehicle; b) classifying each structure into familiessuch that all structures in each family form an experiment over aparticular attribute; and c) for each family, determine which attributesare to be extracted forr the product layout.
 34. A method in accordancewith claim 33 wherein the families include a family comprising neststructures for exploring basic defectivity over a selected number ofline widths and spaces.
 35. A method in accordance with claim 33 whereinthe families include a family comprising snake and comb structures forexploring yield over a predetermined range of line widths and spaces.36. A method in accordance with claim 35 wherein the predetermined rangeof line widths and spaces include relatively large line widths next torelatively small spaces and relatively large interline spaces next torelatively small line widths.
 37. A method in accordance with claim 33wherein the families include a family comprising Kelvin criticaldimension and van der Pauw structures for exploring critical dimensionvariation across line density, width and spacing.
 38. A method inaccordance with claim 33 wherein the families include a familycomprising border structures for exploring the effect of various opticalproximity correction schemes on yield.
 39. A system for determining andranking yield loss mechanisms given characterization vehicle data andextracted layout attributes.